Microsemi Corporation announced its newest network synchronization integrated circuit (IC) product family for Synchronous Ethernet (SyncE) and IEEE™ 1588 timing and line card applications. Targeted for upcoming 5G wireless equipment and network infrastructure, the new product family provides advanced phase measurement and adjustment capabilities which simplify next-generation transport and wireless equipment design. These capabilities also enable equipment to achieve the stringent phase alignment requirements which are down to 130 nanoseconds (ns) across the entire network.
As next-generation networks will move greater amounts of data providing increased connectivity and must do so with lower latency and at a lower cost, Microsemi's new network synchronization IC product family provides the feature set necessary to address these challenges. The devices' precise timing capabilities to monitor, measure, tune and calibrate to the picosecond enable equipment manufacturers to address the tenfold increase in phase alignment accuracy required by 5G networks.
"The precise time capabilities of these new devices directly address the growing constraints put on our customers by next-generation networks," said Maamoun Seido, vice president and business unit manager for Microsemi's timing products. "Our new network synchronization IC product family strengthens our leadership position in the market by leveraging our deep expertise to solve these difficult 5G requirements with advanced features and technologies."
According to market research firm IHS Markit, worldwide acceleration in 5G developments has pushed the 5G forecast substantially from $59 million in 2018 to $11.3 billion in 2022. Microsemi's new product family is ideal for a variety of 5G applications, including 5G baseband, radio units, distributed units and centralized units.
These new devices can also address the demands of mobile fronthaul/midhaul/backhaul, including microwave/millimeter wave and service provider switches and routers.
Key Features
· Up to three independent DPLL channels
· Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
· Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
· Split oscillator option lowers cost, lowers jitter, and provides redundancy
· Excellent jitter performance of <300 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
· Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
· One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
· 8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
· Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
· Up to three programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
· Accepts up to 10 differential or 10 single ended input references
· Full reference monitoring of electrical failures
· Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
· Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
· Easy Configuration and dynamic programming via SPI/I2C interface
· Factory programming available
· Operates from a single crystal resonator or clock oscillator
Applications
· Line card timing function for carrier network equipment compliant to ITU-T G.8262, G.8273.2, G.8273.4
· Communications systems timed by any combination of Synchronous Ethernet, IEEE 1588 PTP, or GPS/GNSS
· 5G wireless CU, DU, and RU systems
· 5G systems with precise time requirements driven by advanced services such as carrier aggregation, coordinated multipoint, OTDOA location, etc.
· Carrier routers, access aggregation, wireless backhaul,
· SONET/SDH systems
